Today the IEEE 1149.1 (JTAG) Test Access Port (TAP) interface is used for many different applications. While initially designed to provide a serial test interface on ICs to facilitate board testing, the TAP interface now serves as a serial interface for additional IEEE standards for such things as emulation, trace, and debug (IEEE 5001) of ICs and cores, mixed signal testing (IEEE 1149.4) of ICs and cores, advanced IC to IC interconnect testing (IEEE 1149.6), embedded core testing (IEEE 1500), and in-system-programming of circuits in ICs and cores (IEEE 1532).
An IC may contain many embedded 1149.1 based TAP architectures (TAP domains). Some of these TAP domains are associated with intellectual property (IP) core circuits within the IC, and serve as access interfaces to test, debug, trace, emulation, and in-system-programming circuitry within the IP cores. Other TAP domains may exist in the IC which are not associated with cores but rather to circuitry in the IC external of the cores. Further, the IC itself will typically contain a TAP domain for operating IC level test, debug, trace, emulation, and in-system-programming, as well as the boundary scan register associated with the IC's input and output terminals.
From the above, it is clear that TAP domains are being used in ever growing numbers in devices, such as ICs and cores, for test, debug, trace, emulation, in-system-programming, and other types of operations.
The present disclosure describes novel methods and apparatuses for using a TAP Domain's test mode select (TMS) and test clock (TCK) interface terminals as a general purpose serial Input/Output (I/O) bus. According to one aspect, the TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, and (3) between a first and second core circuit within an IC. The use of TMS as a clock signal and TCK as a data signal does not effect the standardized operation of 1149.1 TAP Domains, since the TMS clock and TCK data operations occur when the TAP Domains are in a steady state.
FIG. 1 illustrates a simple example of an IEEE 1149.1 TAP domain 102. The TAP domain includes a TAP controller 104, an instruction register (IR) 106, at least two data registers (DR) 108, and multiplexer circuitry 110. The TAP domain interface consists of a TDI input, a TCK input from an input buffer 116, a TMS input from an input buffer 118, a TRST input from an input buffer 120, and a TDO output.
An input buffer will exist on the TDI input if the TAP Domain is used by itself in an IC or if it is the first TAP Domain in a series of serially connected TAP Domains in an IC. Also an output buffer will exist on the TDO output if the TAP Domain is used by itself in an IC or if it is the last TAP Domain in a series of serially connected TAP Domains in an IC.
In response to TCK and TMS control inputs to TAP controller 104, the TAP controller outputs control to capture data into and shift data through either the IR 106 from TDI to TDO or a selected DR 108 from TDI to TDO. The data shifted into IR 106 is updated and output on bus 114 to other circuits, and the data shifted into a DR 108 is updated and output on bus 112 to other circuits. DR 108 may also capture data from other circuits on bus 112 and IR 106 may capture data from other circuits on bus 114. In response to a TRST input to the TAP controller 104, the TAP controller, IR and DR are reset to known states. The structure and operation of IEEE 1149.1 TAP domain architectures like that of FIG. 1 are well known.
FIG. 2 illustrates the state diagram of the TAP controller 104. All IEEE 1149.1 standard TAP controllers operate according to this state diagram. State transitions occur in response to TMS input and are clocked by the TCK input. The IEEE 1149.1 TAP state diagram is well known.
FIG. 3 illustrates an example scan path system 302 where a number of TAP domain 102 interfaces of ICs 306-312 or embedded cores 306-312 within ICs are connected together serially, via their TDI and TDO terminals, to form a scan path 302 from TDI 304 to TDO 307. Each TAP domain 102 of the ICs/cores 306-312 are also commonly connected to TCK 314, TMS 316, and TRST 318 inputs. The scan path's TDI 304, TDO 307, TCK 314, TMS 316, and TRST 318 signals are coupled to a controller 320, which can serve as a test, debug, trace, emulation, in-system-programming, and/or other application controller. While only four TAP domains 102 of ICs/cores 306-312 are shown, any number of IC/core TAP domains may exist in scan path 302, as indicated by dotted line 322. The scan path 302 arrangement of IC/core TAP domains is well known in the industry.
As seen in FIG. 3, if data is to be input to TAP domain 102 of IC/core 312 from controller 320 it must serially pass through all leading TAP domains of ICs/cores 306-310. Further, if data is to be output from TAP domain 102 of IC/core 306 to controller 320 it must pass through all trailing TAP domains of ICs/cores 308-312. Thus a data input and/or output latency exists between a target TAP domain in scan path 302 and controller 320, due to having to serially traverse intermediate TAP Domains. To further exacerbate the problem, the shifting frequency of the scan path 302 is limited by the slowest shifting TAP domain in the scan path.
For example, if a target TAP domain (i.e. the one where data is to be input to or output from) can shift at 100 MHz, but one or more of the other TAP Domains that need to be serially traversed during the input or output operation can only shift at 10 MHz, the data transfer between the controller 320 and the target TAP domain will be limited to the frequency of the slower TAP domain, i.e. 10 MHz. Due to the above mentioned data latency and shift frequency limitation problems, it is clear that the data communication bandwidth between a target TAP domain and controller 320 is not optimized.
As will be seen later, the present disclosure provides a way to eliminate the above mentioned data latency and shift frequency limitation problems by making use of the direct TMS 316 and TCK 314 connections between the TAP domains of ICs/cores 306-312 and controller 320. Having a direct connection for data input and output between the controller 320 and the TAP domains 102, via the TMS and TCK connections, provides improved data communication bandwidth during test, debug, trace, emulation, in-circuit-programming, and other types of operations. Further, using the direct TCK and TMS connections as a serial bus for data input and output between controller 320 and TAP domains 102 only involves the controller and the targeted TAP domain. Non-targeted TAP domains are not aware of or effected by the direct TMS and TCK communication.